Over-Connect / Via bug

Upverter Support Layout Editor
#1

I found a bug (again odd that no none else has gotten this). When I place a via connect to a specific net which goes through 2 pours, and not even connected to one of the pours though the via properties it still connects to that pour even though its not supposed to connect to the layer nor the net.

Here’s a few pictures (tried uploading but they keep going into oblivion when I uploaded them)
View of the error in the layout editor
View of the via settings showing connected net
As you can see the via isn’t connected to the ground layer which has the ground pour. Its connected to VDD_12R0 which is the pink pour, but yet its giving me this error.
to get rid of the error i have to delete the via and reload the editor (otherwise a weird outline persists which the drc thinks its still there)

Thanks!

Further data:
Since I have to manually regenerate the pours every time i do anything and the DRC checker which doesn’t require manual operation, constantly naggs at me until i re-pour, the issue persists for a bit, i have to refresh the screen for the errors to go away or explicitly click the ignore the constraint. I suppose its not so much a bug but a feature change/correction to help sanity.

Further Observations:
Must be a bug. Via’s are associated with nets, pours are being regenerated, refreshing page (after waiting for save), ignoring the constraint. Still gives me the nagging overlay. I would remove the constraints layer, but I’m still working with my rats. Could the rats be their own layer? That would make it easier to ignore errors that aren’t errors until you really want to check them.

#3

The DRC checker runs too slowly to run it after every pour, so it runs in the background. When things are working correctly, it eventually catches up. This can take many minutes on our design, which is only 5x5cm.

Sometimes things don’t work correctly, and the DRC checker thinks it is up to date, when it isn’t. When a bogus constraint violation is still there the next day, I know it will never go away on its own. These would go away eventually when I swapped one of the involved parts with an identical part or delete a via, and put an identical one back. I suspect any change to the design in the area of the nagging overlay would work, but I’ve been doing the swap a part with its self. Then I would exit the tool, and see if the nagging constraint violation was still there. If it was, I would wait half an hour, and try the exit upverter and restart. Then the problem would be gone.

Some bug trained me to delete vias and create new ones, rather than to just move vias. I’ve forgotten what the bug was, but it didn’t happen very often, but when it did, it was a pain. Well more than 95% of the time, moving vias just works. I think it involved accidentally connecting nets. If a via touched the wrong net or pour while it was being moved, sometimes the tool would not forget, even after the via wasn’t touching the net.

#4

Am I seeing another occurrence of the same bug in this design, where I have a constraint violation for the +3.0V net being over-connected? I don’t think it’s over-connected at all. Have tried refreshing. Have tried deleting and replacing vias.

https://upverter.com/eda/#tool=pcb,designId=1ecdbd614ba312f9

(Open source design, all should be able to view it.)

#5

Take a look at D11. Looks like the schematic net is unconnected. When you connect it on the layout side it throws the violation.

#6

Thanks dude! You have good eyes! Apologies for the bug false accusation, Upverter people.

#7

No sweat.

It kinda is a bug because I think there’s supposed to be a DRC violation there as an “unconnected net” or something. If it’s not a violation it should be - it’s like a hanging chad :wink: